1. Field of the Invention
The present invention relates to a process flow for producing non-volatile memories with differentiated removal of the sacrificial oxide, and in particular to an NO-DPCC (double short-circuited poly) process or for any memory device in which a first layer of polysilicon is removed.
2. Discussion of the Related Art
In the conventional process flow for producing non-volatile memory devices of the flash type, immediately after a step in which a field oxide is generated, after a step in which the layers suitable for forming the active areas (HARD MASK) are removed, after a step in which a thermal oxide about 300-500 A thick is generated and after a step in which implants of boron in the memory cells (EPM) in the matrix area have been made, this thermal oxide, also called sacrificial oxide, is completely removed by a blanket attack and with it also all the impurities and residues left from the previous operations. Therefore the sacrificial oxide is removed both from the area of the memory matrix and from the circuitry area.
In an NO-DPCC circuit, the flash memory cells consist of a first layer of polysilicon, called polyI, and a second layer of polysilicon, called polyII, isolated by a dielectric layer, called interpoly dielectric. After the formation of a tunnel oxide, of the polyI and the interpoly dielectric over the whole surface of the device, said layers must be completely removed from the circuitry area before the successive formation of the polyII.
A problem that can occur during the interpoly dielectric removal step and in particular of the polyI is that damage can be made, in the circuitry zone, of the area below, due to an overattack and a possible breaking of the tunnel oxide, caused, for example, by machine process imprecision.
In view of the state of the art described, an object of the present invention is to prevent this breaking of the tunnel oxide from occurring during the attack of the interpoly dielectric and the polyI.
According to the present invention, this and other objects are achieved by a process flow including the steps of:
(a) a step of growth of a layer of sacrificial oxide on a substrate of silicon on said matrix area and said circuitry area;
(b) a step in which a layer of sacrificial oxide is removed by means of an attack in said matrix area;
(c) a step of growth of a layer of tunnel oxide on said matrix area and said circuitry area;
(d) a step of deposition a first layer of polysilicon;
(e) a step of formation of a layer of interpoly dielectric after said first layer of polysilicon on said circuitry and matrix areas;
(f) a step of attack to said layer of dielectric in said circuitry;
(g) a step of attack to said first layer of polysilicon in said circuitry area;
(h) a step of attack to said layer of sacrificial oxide and on the tunnel oxide by means of a wet attack in said circuitry area.
Thanks to this invention such oxide can be removed in the circuitry area while protecting the layers below from any damage caused by attacks previously made without introducing any additional step to the memory cell implementation process. In this manner the active areas of the circuitry are protected from the danger of oxide breaking, thus avoiding the degradation of the quality of the circuitry oxides and, in addition, increasing the level of reliability of the device itself.